1. Field
The present disclosure relates to systems and techniques for calibrating an integrated circuit to an electronic component.
2. Background
Integrated circuits have revolutionized the electronics industry by enabling new applications which were not possible with discrete devices. Integration allows complex circuits consisting of millions of electronic components to be packaged into a single chip of semiconductor material. In addition, integration offers the advantages of fabricating hundreds of chips on a single silicon wafer, which greatly reduces the cost and increases the reliability of each of the finished circuits.
Integrated circuits are widely used today in electronic devices to implement sophisticated circuitry such as general purpose and specific application processors. A controller integrated onto the chip may be used to interface the various processors with off-chip components, such as external memory and the like. Clocks generated by the controller may be used to access these off-chip components. These clocks should operate at a specific nominal speed, within a certain allowed tolerance, to ensure that the controller can communicate with the off-chip components under worst case temperature and voltage conditions.
Due to processes inherent in the silicon wafer fabrication process, a set of chips generated from a single wafer may fall into a range of different process speed ratings. Depending on the application, some manufacturers are forced to discard slow chips and fast chips that are outside of the nominal tolerance range. This leads to large amounts of waste, which can be very costly.
In an attempt to preserve those portions of the wafer that do not produce nominal chips, some manufacturers engage in a method of speed binning, in which the various chips produced from a single wafer are tested and batched according to their graded process speed. This method of batching chips according to their speed is time consuming and costly. Further cost is incurred as a result of selling slow chips and fast chips at reduced prices.
Delays are used to implement the timing needed to ensure error-free communication between the integrated circuit and external component that make up an electronic device. They are a function of many factors, including the speed and voltage of the integrated circuit and the speed of the external component. These delays can be determined, for example, using a calibration process that tests such communications and then derives delays from test results. Variations in such parameters across many integrated circuits and external components can result in a predetermined delay not being optimal for a given electronic device. Yet, it is not practical to know beforehand the actual speed and voltage of each integrated circuit or the speed of the external component. Therefore, at best, chip makers have had to settle for determining a program delay that will work without error across anticipated ranges of such parameters, even though such predetermined delays would knowingly not be optimal for many electronic devices.